Many high volume, high speed printed circuit boards distribute differential clock signals with a differential clock driver. Besides the normal function of providing clocking (or synchronization) signals to the various integrated circuits, the outputs of the differential clock driver can be used to generate a signal to activate or change a function within a device that uses the differential clock signal as an input. For example, a differential clock driver would typically generate two clock output signals that are 180 degrees out of phase with each other. These two clock signals could be used to provide synchronization for a phase-locked loop (PLL), a microprocessor or another signal processing device or circuit.
Under normal clocking (or synchronizing) operation, the two clock signals would always be in opposite states and would never simultaneously be in the same logic state. If the clock driver were to force the two clock signals to a logic state that was outside the normal clocking operation, this condition could be detected and then as the result of this detection some action could be initiated within the device that uses the two clock signals as inputs. For one pair of clock signals, there are three possible logic states that would be outside the normal clocking operation. These three states are both clock signals low, both clock signals high, or both clock signals tri-stated. For multiple pairs of clock signals, there would be other possible logic states that are outside the normal clocking operation which could be detected. One example of an action that could be initiated by this detection would be to power down a portion of an integrated circuit such as a PLL.
A problem with current clock signal detection schemes is that they use a frequency detection circuit. Under current clock signal detection circuits, if the frequency of a clock signal drops below a predetermined threshold, the circuit will generate a deactivation signal. These frequency detect circuits are somewhat more complicated than simply determining the logic state of the clock input signals. Because of this complexity, the frequency detect circuits require more electronic devices to implement, require more silicon area, and draw more power supply current. Another disadvantage with the clock frequency detect circuit is that once the differential clock signal has dropped below a certain threshold frequency, there is a significant amount of lag time until the output of the frequency detect circuit indicates that the frequency is too low. The lag time for a circuit that determines the logic state of the clock inputs is much shorter.
Accordingly, it is desirable to provide an improved clock signal detection circuit.